The present invention relates to a clock synchronizing circuit and, more particularly, to a clock synchronizing circuit for synchronizing, in a network, a clock signal to be generated in a terminal node to a clock signal sent from a clock feeding device included in a master node.
It is a common practice with a large scale digital communication network to implement a network synchronizing system with a master-slave scheme. In a master-slave synchronizing system, a master node generates a clock signal with a clock generating device thereof and sends it to a terminal node. The terminal node generates a clock signal based on the received clock thereinside. A conventional clock synchronizing circuit using the master-slave scheme has a phase difference detector for producing a voltage signal representative of a phase difference between an input and an output clock signal, a low pass filter, and a voltage controlled oscillator (VCO) for producing a predetermined clock signal matching the voltage signal. The problem with such a clock synchronizing circuit is as follows. The frequency of the output clock signal is controlled on the basis of the phase difference between an input and an output clock signal. Hence, when the frequency of the input clock signal, which is the reference, is changed or interrupted for a moment due to jitter or similar cause, the phase difference detector detects the change or interruption and feeds the resulting output thereof to the VCO as a phase difference signal. As a result, the VCO outputs a clock signal proportional to the change in the frequency of the input clock signal. Moreover, in an application of the kind requiring a stable output clock signal, uncontrollable phase deviations occur since the output clock signal is controlled on the basis of a variation width produced by a temperature compensation circuit which is included in the VCO.